The present invention generally relates to complimentary metal-oxide semiconductors (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to vertical transistor technology.
The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (NFET) and p-type field effect transistors (PFET) are two types of complementary MOSFETs. The NFET uses electrons as the current carriers and with n-doped source and drain junctions. The PFET uses holes as the current carriers and with p-doped source and drain junctions.
The FinFET is a type of MOSFET. The FinFET is a multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The “fin” refers to a semiconductor material patterned on a substrate that often has three exposed surfaces that form the narrow channel between source and drain regions. A thin dielectric layer arranged over the fin separates the fin channel from the gate. Since the fin provides a three dimensional surface for the channel region, a larger channel length may be achieved in a given region of the substrate as opposed to a planar FET device.
As CMOS scales to smaller dimensions, vertical FET devices provide advantages. A vertical FET often comprises an active source/drain region layer arranged on a substrate. A bottom spacer layer is arranged on the active source/drain region layer. The channel region of the FET device is arranged on the bottom spacer layer. The channel region may include any number of shapes including a fin shape.
The gate stack is arranged on the bottom spacer layer and around the channel region. A top spacer layer is arranged on the gate stack. The spacers are used to define the channel region in active areas of a semiconductor substrate located adjacent to the gate.
Device scaling drives the semiconductor industry, which reduces costs, decreases power consumption, and provides faster devices with increased functions per unit area. Improvements in optical lithography have played a major role in device scaling. However, optical lithography has limitations for minimum dimensions, which are determined by the wavelength of the irradiation.